AMD’s Thunderbird Soars into Marketplace

Advanced Micro Devices Corp. ( released two new processors: a new version of its Athlon processor and a value-oriented processor, the Duron.

The new Athlon, formerly code-named Thunderbird, features on die Level 2 (L2) cache. Previous Athlons had L2 cache off of the chip, but in the same processor unit. L2 cache stores instructions inside the bus, provide the processor with a constant stream of instruction. Placing L2 on the chip die reduces the latency between the processor and the L2 memory, thus improving performance.

Because previous Athlons did not have on die L2 cache, it became a point of negative comparison between the Athlon and the Pentium III. The new versions of Athlon have 256 KB of L2 cache, and 128 KB of L1 cache, all located on the die.

Analyst Nathan Brookwood of Insight 64 group, based in Saratoga, Calif., says adding L2 cache to the die gives AMD benefits in addition to performance gains. First, manufacturing is less expensive because memory and processors are created in the same process. Buying memory to coordinate with processors running at up to 1 GHz presents an additional problem for having L2 off die. Also, Brookwood says, "There’s circuit design problems getting electrons outside the cartridge and into the chip." On die cache is the best solution for today’s high-speed chips.

With the new Athlons, AMD introduced new packaging -- the Socket A design. The first generation Athlons were shipped in the Slot A design. The processor and L2 memory were contained in a plastic cartridge that snapped into a slot on the motherboard. Now that the L2 cache is on the chip, AMD is using the socket design, where pins are inserted directly into the chip. AMD is shipping both Socket A and Slot A Athlons so OEMs can ship the new chips as soon as possible.

Athlon’s 200 MHz front side bus (FSB) holds an advantage over Pentium III’s 133 MHz maximum FSB. Pentium III, however, still has some advantages for enterprise users. Athlon has gained a reputation as a quality processor for desktop applications, but has seen little action in enterprise servers. "They’ve yet to see credibility on four-way and eight-way servers," Brookwood says.

This may be partly due to the lack of chipsets for SMP Athlon motherboards. "Intel makes it a little bit easier for SMP," Brookwood says. While Intel allows multiple Pentiums and Xeons to connect to the FSB through a single connection, AMD has followed the Alpha by requiring Athlons to have independent connections to the FSB. Brookwood expects to see SMP chipsets for the Athlon based off of the Alpha design. "It should be an absolutely trivial task" he says.

AMD’s Duron line may be a low-cost proposition, but the only sacrifice AMD made was in abbreviating the L2 cache to 128 KB. Like the new Athlons, the Durons sport a 200 MHz FSB, Socket A package design, and potential speeds up to 1 GHz and beyond. The current Durons come in 600 MHz, 650 MHz, and 700 MHz models.

The smaller L2 cache does result in poorer performance, but Brookwood says Duron is capable for most business applications. "An awful lot of business users don’t need the maximum speeds for desktops," he says. Large L2 cache is useful for high-throughput servers and computation-intensive applications such as graphics. Users who push their computers by changing fonts and checking e-mail, don’t need the extra memory.

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