In-Depth

IBM Tries to Do More With Less

Big Blue to push small servers as alternatives to competitors' larger SMP systems

• By Stephen Swoyer
• 02/25/2003

IBM representatives say the move is a harbinger of things to come. VP of pSeries marketing Karl Freund says that new technology in IBM’s forthcoming Power5 chip, slated to ship next year, will enable the next-generation RISC microprocessor to achieve the performance of as many as four of today’s Power4 chips for many business tasks.

The upshot, he claims, is that IBM’s smaller SMP systems will increasingly be able to bottom feed on the larger SMP offerings of competitors.

There are several reasons for this, Freund suggests, including the terms of most enterprise licensing agreements, which typically specify per-processor capacity licensing charges. A small SMP system that is able to approximate—or, in some cases, equal—the performance of a large SMP box will do so at a fraction of the software licensing costs, he argues. “When you deliver more performance per processor, you save on not only the system, but also the software. All of the subscription services … [are] priced based on the number of processors. So if we can deliver the same performance on a 630 that Sun does on a V880, we’re probably going to win over the customer based on the software pricing.”

In particular, IBM is targeting Sun, which markets an UltraSPARC III processor that currently trails the performance of Big Blue’s own Power4—as well as the PA-RISC 8800 from Hewlett-Packard Co. and SPARC64 from Fujitsu, among others—in most uni-processor benchmarks. Says Illuminata analyst Gordon Haff: “UltraSPARC is generally viewed as being a bit behind some of the competitive architectures, IBM’s Power certainly.”

Sun’s value series V-class V480 and V880 systems are powered by its 900 MHz UltraSPARC III processors, but the company has refreshed its high-end SunFire systems with UltraSPARC III chips running at 1.2 GHz. Sun also has a 1.05 GHz version of UltraSPARC III.

IBM’s Freund says that a four-way pSeries p630 populated with new Power4+ chips is 30 percent faster than a p630 outfitted with vanilla 1.4 GHz Power4 chips. Moreover, he suggests, the Power4+-equipped p630 is better suited to assume the workloads of larger competitive systems—such as a Sun V880—for many business tasks. “Today, with this level of performance, we expect the 630 to be chosen over the V880 as often as it will be chosen over the V480.”

Going forward, with the Power5, he anticipates, IBM’s value proposition will become more compelling. Power5 will incorporate Big Blue’s FastPath technology, which offloads the processing of common tasks usually accomplished in software, such as virtual memory subroutines. More significantly, Power5 will support IBM’s simultaneous multi-threading (SMT) technology, which, Freund says, effectively enables it to do the work of a much larger SMP system. “A single-processor Power5 system will probably be able to do the job of about a four processor system today.”

Sun has indicated that it will also introduce a version of SMT in its forthcoming UltraSPARC IV chip (http://esj.com/news/article.asp?EditorialsID=307).

In an October 2002 interview, Sun VP of marketing Andy Ingram said that UltraSPARC IV would integrate advanced multi-threading support, which he compared to the "hyper-threading"—SMT—technology that Intel Corp. introduced last year in its Pentium 4 chips. At the time, Ingram claimed that UltraSPARC IV's SMT technology would permit a "processor [to] work on multiple instruction streams, multiple processes, at a single point in time."

Power4+ for High-End pSeries?

IBM introduced the Power4 in its top-of-the-line 32-way pSeries p690 in late 2001, but first started shipping the Power4+ in its eight-way pSeries p650, released in November 2002. Freund says that Big Blue made a conscious decision to attack the high-end with the Power4, and has sought to bring the Power4+, which is cheaper to manufacture, first to its midrange and low-end offerings. “The initial Power4 architecture was designed to deliver extreme performance for high-end SMP. It’s the Power4+ that allows us to get this [extreme performance] with these kinds of lower prices.”

Freund declines to indicate when IBM’s pSeries p670 (a 16-way system) and the high-end p690 would be refreshed with Power4+ processors. “I couldn’t really get into the sequencing, but I can say that we will support the Power4+ architecture across the entire range of our product line.” He confirms that Big Blue’s high-end systems would probably be outfitted with Power4+ chips sometime this year.

Sun to Preview SMP on a Chip

At its analyst conference in Burlington, Mass. this week, Sun is expected to provide details about a new multicore technology that will allow it to combine dozens of discreet processors to form a single large chip.

The Unix kingpin last year acquired Afara Websystems, a start-up that pioneered a method of linking processor cores. Afara Websystems’ multicore chip technology is analogous to the SMP technology that connects multiple processors to power a single server.

The technology Sun plans to disclose proposes combining multiple cores of simplified processors, typically clocked slower Sun’s larger UltraSPARC III chips, to form a single chip grid that is able to more effectively distribute workloads. The idea is to enhance application performance by more efficiently distributing threads across each of the discrete processor cores.