Microprocessor Roadmaps Blur

Chips from IBM, Sun, and HP have many of the same features

In the first quarter of this year, Hewlett-Packard Co., IBM Corp., and Sun Microsystems Inc. announced significant updates to their microprocessor roadmaps. In a number of respects—chip multi-threading, multi-core processor design and, of course, higher clock speeds—all three vendors are touting variations, at least, on the same themes.

At this point, IBM has only said that it will deliver Power5 “sometime in 2004." Big Blue has been good about meeting its delivery timetables—Power4 and Power4+ both shipped on schedule—and at this point, there’s no reason to doubt this claim. Moreover, last month IBM announced (http://www.esj.com/News/article.asp?EditorialsID=425) that it had successfully booted a Power5 system. Last week, an IBM representative disclosed that Big Blue has a 32-way test system running its next-generation chip. At this point, anyway, Power5 appears to be on track.

Power5 is expected to incorporate several important design enhancements, including a chip multi-threading technology that IBM calls simultaneous multi-threading (SMT). Karl Freund, VP of pSeries marketing for IBM, says that as a result of SMT, Power5-based systems will be able to accomplish substantially more work than their predecessors. “A single-processor Power5 system will probably be able to do the job of about a four processor system today.”

IBM is also building a technology that it calls “FastPath” into its next-generation microprocessor. FastPath brings ASIC-like functionality to Power5, making it possible to offload the processing of common tasks usually accomplished in software—such as TCP/IP processing.

Right now, Power4—which supports two microprocessor cores on a single chip—is the only multi-core chip design on the market. Power5 will initially ship in a similar form-factor; it is expected to appear in tandem with IBM’s forthcoming 64-processor “Squadron” system, also slated for delivery some time next year. IBM’s current top-of-the-line iSeries 890 and pSeries p690 “Regatta” systems support up to 32 Power4 processors. At this point, IBM hasn’t disclosed at what speed Power5 will run, although analysts anticipate that the chip will debut in the 1.5 GHz range.

During its analyst briefings last month, Sun also announced (http://www.esj.com/News/article.asp?EditorialsID=436) an aggressive processor roadmap that stresses—not surprisingly—multi-core chip development and chip multi-threading. Unlike IBM’s SMT implementation in Power5, however, Sun’s multi-threading initiative—which the Unix giant calls chip multi-threading (CMT)—draws from its work in designing scalable multi-core chips that aren’t exclusively based on its current efforts with UltraSPARC.

Sun’s long-awaited (and oft-delayed) UltraSPARC IV microprocessor has been promised for late this year or early next year. In the interim, Sun will ship a new version of UltraSPARC IIIi that brings the performance and reliability, availability, and security features of its high-end S-series processors to the midrange I-Series chips that populate its one- to four-way servers.

Starting with UltraSPARC IV, Sun will deliver a multi-core chip with two microprocessor cores and integrated CMT technology. UltraSPARC IV will also be available in a blade-only version—code-named “Gemini”—that is expected to ship in 2004. It, too, will be a dual-core chip.

UltraSPARC V is still slated to appear in 2005, Sun says, and will support roughly five times the throughput of Sun’s existing processors. It will include support for version 3 of Sun’s VIS Instruction Set 3, which should accelerate encryption and other applications. UltraSPARC V will also support at least two discrete modes of operation, enabling it to be optimized for business or high-performance computing applications.

Much of Sun’s CMT technology is linked to a radical new multi-core design that it expects to introduce in a shipping product—code-named “Niagara”—by 2005. Niagara will forego much of the complexity of today’s single-threaded UltraSPARC chips in favor of multiple chip cores—eight in all, which can each run four threads (for a total of 32 threads)—that support a more efficient distribution of application threads. Niagara also boasts integrated network, encryption, and memory features. The upshot, Sun claims, is a 15x throughput improvement over current UltraSPARC processors.

Sun has indicated that at some point after 2005, it will merge Niagara with UltraSPARC to create a processor that is 30 times faster than its current top-of-the-line 1.2 GHz UltraSPARC III.

For its part, HP is expected to deliver the successor to its PA-8700 chip, the PA-8800 processor, this year. PA-8800 is a dual-core design that exploits a bus topology that is electrically compatible with Intel Corp.’s Itanium microprocessor. It is expected to debut at speeds in the neighborhood of 1 GHz.

At last month’s Intel Developer Forum, HP representatives disclosed that by mid-2003 it will start shipping its sx1000 chipset—formerly code-named “Pinnacles”—that supports up to 64 Itanium or PA-RISC processors. Because PA-8800 will be a dual-core chip, however, Pinnacles will be able to support as many as 128 PA-8800 processors. Itanium isn’t expected to be available as a dual-core chip until sometime in 2005, but later on this year, HP will release a new packaging technology—dubbed mx2—that will allow it to double-up Itanium chips. The result: 128 Itanium processors on a single Pinnacles-powered server.

HP has two additional iterations of PA-RISC—PA-RISC 8800 and PA-RISC 8900—that will carry it through 2006. After that, the company has said it will ship Itanium-only systems. If demand for Itanium hasn't materialized by that time, HP will be at a competitive disadvantage vis-à-vis Sun and IBM, whose UltraSPARC and Power development projects will continue apace.

About the Author

Stephen Swoyer is a Nashville, TN-based freelance journalist who writes about technology.