Q&A: IBM Talks Power5
With Power5, IBM introduced Simultaneous Multithreading, in which each of the processors on the chip looks to the software like two processors. The technology offers 40 percent more performance.
At the Hot Chips semiconductor design conference held last week at Stanford University, IBM Corp. presented a paper about its forthcoming Power5 processor, which it expects to introduce next year.
We spoke recently with Joel Tendler, director of technology assessment in IBM’s systems group, who was attending the conference.
Tell us about Power5. How is it coming along?
We’re pretty far along with it. We’ve had it running on AIX, Linux, and OS/400 in the lab for months now. We’re on track to bring this to market next year, on schedule.
The big news about Power5 from Hot Chips is discussion of Simultaneous Multithreading. What is it and how does it work?
Remember that Power4 was the first chip that had two processors on a single die, which we called chip multiprocessing. Since that time, Power4 has been the premier microprocessor. It has been and continues to be the fastest microprocessor from a frequency perspective.
With Power5, we’re introducing something that we call Simultaneous Multithreading, or SMT. What this means is that each of the processors on the chip looks to the software like two processors, so that on each chip, we effectively have four microprocessors.
What’s the advantage of SMT? Does it effectively offer twice the performance of the existing chip cores?
On chips today, the execution engine is lightly utilized—usually only about 25 percent utilization. With SMT, we allow each processor to execute instructions independently and concurrently. By that approach, we’re seeing that we’re gaining 40 percent more performance.
It’s more than that, though. Some of the things that we’ve done for SMT even have benefits for what we call single threaded mode. Our enhancements to make SMT work improved the performance of single threads for applications like platform computing, which will see performance gains even on Power5 because of what we’ve done to enhance the chip.
And also, because of the way that we’ve engineered it, by trying to get more work done, we’ve put in a hardware facility to prioritize the two threads. We’ve created dynamic power management so that power can be dynamically moved to where it’s needed, with no performance impact
You’ve said that there’s no API for SMT, and that it will tend to run some applications better than others.
It’s totally transparent to the software and to the application. To the software, it looks like each processor looks like it’s two processors. Although the OS does need to know that there are more processors.
Intel last year released a similar technology, called hyper-threading, with its Pentium IV processor. Unfortunately, Microsoft’s Windows NT operating system detected the hyper-threaded chips as two processors, leading to issues on systems that were licensed for a specific number of processors. Is it possible that older versions of application software for AIX or OS/400 could do the same?
The charging protocols are determined by each of the software vendors, so I really can’t say. Right now, it’s clearly our intent to not have them do that, and we don’t anticipate that that will be a problem.
There’s been a move recently to reduce the power consumption of systems processors, especially for server blades. Sun, for example, last year introduced a cooler version of its UltraSPARC III processor that dissipated about 60 watts of heat. How do the new enhancements you’re making to Power5 affect the amount of power that it dissipates?
Right now, on a per-processor basis, Power4+ is the most efficient among the 64-bit processors. You can compare it to UltraSparc III, or if you compare it relative to Itanium, which takes more than 100 watts, and Power4+ is at 60 watts. So in comparison with Sun, we’re comparable. We’ve added new power management capabilities, so that you’ll be able to get control of it more. You always like to run it cooler, but right now that’s not a problem for us.
What clock speeds do you expect to hit with the Power5 architecture?
Eventually, we expect to hit 3 GHz by 2005. We’re using copper silicon insulator [130 nm] for the first generation, and we will continue to, that’s one of the things that allows us to be as power efficient as we can. By 2005, we will go to 90 nm so that we can gain even more advantages, such as faster and lower power consumption.
Power4 was the first multi-core chip, but you’re content to stay with two-chip cores with Power5. Can we expect the incorporation of more-than-two-chip cores in future Power processors?
We obviously continuously look at it, but right now, we don’t see it going through that. We don’t see it going through more than two threads per core. In our mind, it isn’t justified. It may sound good, but there’s no value there. As you add more, you get less back. It’s like a law of diminishing returns, so you’ve got to draw that balance.
Stephen Swoyer is a Nashville, TN-based freelance journalist who writes about technology.