Intel Firms Up Date for Profusion

Profusion, the eight-way architecture Intel Corp. acquired in October 1997, will ship in the second quarter.

NEW YORK -- Profusion, the eight-way architecture Intel Corp. acquired in October 1997, will ship in the second quarter. The projection was confirmed by John Miner, vice president and general manager of Intel’s Enterprise Servers Group, at the late March launch of the Pentium III Xeon processor.

Miner, who had hinted two months earlier that Profusion was close to market, also said hardware vendors would probably roll out eight-way server offerings in the third quarter. "It’s the key ingredient for taking the SHV [standard high-volume] concept from the four-way threshold, where it’s been since ’93, to eight-way," Miner says.

A good portion of that time has been spent in anticipation of Profusion. Intel bought Corollary Inc., the specialty chipset vendor that developed Profusion, in 1997. At first, the chipset was expected to come out in the second half of 1998, but Intel was silent and kept Profusion under wraps.

At a show in Germany last month, Compaq Computer Corp. unveiled an eight-way system based on the Profusion architecture. Compaq helped design the I/O with Corollary. Other vendors, including IBM Corp., are formalizing plans to ship systems based on the chipset. James Gargan, IBM’s program director for Netfinity marketing, says the company’s RS/6000 design teams are working on IBM’s version. "We think that 1999 is really going to be the ramping up for 2000 for the move to eight-way," Gargan says.

But the product in hand in late March was Intel’s new Pentium III Xeon processor, featuring higher clock speeds and 70 new instructions Intel calls the Internet Streaming SIMD Extensions. The chip also includes a controversial new serial number that Intel says can be used to improve corporate security. The Pentium III Xeon immediately supports available eight-way architectures, such as those used by Hitachi PC Corp. (www.hitachipc.com) and NEC (www.nec.com), says Patrick Buddenbaum, a product marketing manager with Intel’s Enterprise Server Group.

Intel announced the chip surrounded by a bevy of third-party vendors demonstrating their solutions on the chip and customers supporting the chip. Two groups of vendors were demonstrating eight-way and above systems, but there were no Windows NT demonstrations above four-way. A 16-way demonstration from Data General Corp. (www.dg.com) and Oracle Corp. partitioned an Aviion AV25000 server into three operating systems: an eight-way DG/UX, a four-way DG/UX and a four-way Windows NT.

Most vendors and customers on hand touted improvements in speed. "They performed 32 percent faster," enthused Arthur Kerins, associate director at Barclays Capital, the New York-based investment banking arm of Barclays Bank P.L.C. "Some of our tests moved 60 percent faster. I was blown away." Kerins says he was able to snap Pentium III Xeons into servers that had been running Pentium II Xeons, flash the BIOS and run them.

The initial rev of the chip jumps to 500 MHz. The Pentium II Xeon topped out at 450 MHz. The 500 MHz chip is available in 512 KB, 1 MB and 2 MB Level 2 (L2) cache versions for two-, four- and eight-way servers and workstations. A 550 MHz processor with 512 KB L2 cache for two-way workstations is expected to ship this month, with 1 MB and 2 MB L2 cache versions for four- and eight-way servers expected to be available in the third quarter.

Rob Enderle, a senior analyst specializing in processor issues for Giga Information Group (www.gigaweb.com), says all the performance gains Intel demonstrated were from the 50 MHz jump. "It’s a linear increase with clock speed. You’d get the same thing with the Pentium II [if it were 500 MHz]," Enderle asserts. No one has written applications yet that take advantage of the 70 new instructions Intel included with the chip, he says.

Intel’s Miner emphasizes that the new Xeon chips carry forward the enterprise capabilities introduced in 1998 through the Xeon line: support for multiprocessor systems, optional amounts of L2 cache, integrated reliability features, manageability features and support for Intel’s extended server memory architecture.