Intel Refreshes Itanium with Faster Chips
Will the new Madison chips be a catalyst for an Itanium revolution?
Intel Corp. yesterday refreshed the Itanium 2 processor line with chips based on its third-generation Itanium Processor Family (IPF) architecture, formerly code-named “Madison.”
The next-generation chips retain the Itanium 2 brand, which Intel first established last year when it launched its second-generation Itanium chips (based on an architecture code-named “McKinley").
The new Itanium 2 processors are pin-compatible with their McKinley-based predecessors, so customers who invested in Itanium hardware can replace them with the new chips, which Intel claims outperform their predecessors by between 30 and 50 percent. The new chips debut at a top speed of 1.5 GHz with 6 MB of integrated Level 3 cache.
Itanium—which was code-named “Merced” until Intel re-christened it in 1999—was hyped as a giant-slayer through much of the late 90’s. Many analysts projected that Itanium would be able to hold its own against entrenched 64-bit players such as the UltraSPARC processor from Sun Microsystems Inc. and the Power processor from IBM Corp., among others. When it finally appeared, running at speeds of 700-Mhz and 800-MHz, Merced-based Itanium debuted not with a bang but a whimper.
In light of these difficulties said Nathan Brookwood, a principal with microprocessor consultancy Insight64, Intel revised its expectations for the first iteration of Itanium. “The product was very late. So by the time it hit the streets, it was definitely not awesome,” he pointed out in an interview last year. “You almost have to look at the Merced-based Itanium platform as a proof of concept and software development vehicle much more so than any sort of practical vehicle.”
Itanium 2 changed all of that, Brookwood and other analysts say. It gave Intel a credible 64-bit platform that boasted uni-processor performance that surpassed the architectures of many of its RISC-Unix competitors.
In this respect, says Gordon Haff, a senior analyst with consultancy Illuminata Inc., Intel’s newest Itanium 2 chips further enhance this story. “Madison provides yet another proof point that Itanium performs pretty darn well. I think it should help convince people that from a processor technical perspective, there’s nothing wrong with Itanium."
Haff notes that the revamped Itanium 2 improves upon its predecessor’s stellar performance in several prominent uni-processor benchmarks. “For anyone to suggest at this point that Itanium is a lousy chip architecture, you’ve got an awful lot of numbers out there that you need to argue against. There are an awful lot of benchmarks out there, along with some compelling customer testimonials that suggest that Itanium’s performance is actually quite good.”
In spite of its performance edge, market researchers don’t expect Itanium to displace its established 64-bit competitors any time soon. By 2007, wrote Gartner Inc. analyst Jeff Hewitt last year, Itanium will account for about $4 billion of all revenue in the enterprise server market. By contrast, Hewitt indicated, Sun’s UltraSPARC architecture will generate over $6 billion in revenue. By 2007, Hewitt projects, IBM’s Power architecture will be the 64-bit market leader, with revenues of $8.6 billion.
OEM enthusiasm for Itanium has thus far been limited—at least, among the four vendors that have traditionally dominated the worldwide market for server shipments.
Hewlett-Packard Co., of course, has a bet-the-company commitment to Itanium, but IBM Corp.—which introduced its first Itanium 2-based server in April—and Dell, which is expected to announce its first Itanium 2-powered system this week, were both slow to deliver support for the chip. Sun, for its part, has flatly rejected an Itanium strategy. During a press conference last year, Sun CEO Scott McNealy even dismissed Itanium as “Itanic.”
Limited ISV Support
Since day one, Itanium has been largely a 64-bit play; as a result, the 32-bit performance of the IPF architecture has been problematic. Even when Itanium 2 debuted last spring, the next-generation 64-bit chip was plagued by sub-par performance when executing 32-bit x86 (IA-32) code. Because of the preponderance of 32-bit x86 applications, some analysts have suggested that Itanium’s sub-par 32-bit performance amounts to an Achilles Heel.
To capitalize on this vulnerability, Advanced Micro Devices (AMD) Inc. in April announced its Opteron microprocessor. AMD’s Opteron chips are designed to execute both 32-bit and 64-bit code without sacrificing performance. In response, Intel announced a new software technology, dubbed IA-32 Execution Layer, that will enable a 1.5 GHz Itanium 2 to crunch 32-bit code about as fast as a 1.5 GHz Xeon MP chip. Intel yesterday announced new 2.8 GHz Xeon MP chips.
Intel has said that around 300 applications—including software from Oracle, BEA Systems Inc., and Microsoft Corp., among others—have thus far been developed for Itanium 2. By year’s end, Intel expects that 1,000 Itanium 2 applications will be available.
Big Blue Announces New Intel, Opteron Systems
At the same time as Intel's new Itanium 2- and Xeon MP-relatedannouncements, IBM announced its long-awaited x445 xSeries server. The x445is Big Blue's first entry in the greater-than-16-way space. By the end of2003, the x445 is expected to scale to 32 Xeon MP processors.
IBM also announced that it was resuming shipments of its x450 Itanium2-based system. Big Blue stopped selling the x450 last month after an electrical glitch was found in McKinley-based Itanium 2 chips that could cause them to crash. IBM’s top-of-the-line x450 will be populated with four 1.5 GHz Itanium 2 chips.
IBM last week also announced a new dual-processor rack server powered by AMD’s Opteron chips. Expected to ship later this year, the new system is designed for high-performance computing clusters.
Intel Promises Improved Performancehttp://info.101com.com/default.asp?id=1206
AMD Introduces 64-bit Opteron Chiphttp://info.101com.com/default.asp?id=1153
Growth Spurt: Intel Servers Scale Uphttp://info.101com.com/default.asp?id=680
Mammoth Servers in the Offing http://info.101com.com/default.asp?id=400
Microprocessor Roadmaps Blurhttp://info.101com.com/default.asp?id=830
HP Preps for PA-RISC to Itanium Transition http://esj.com/news/article.asp?EditorialsID=295
Stephen Swoyer is a Nashville, TN-based freelance journalist who writes about technology.